MRC | Criteria | Characteristic |
---|
ADAQ | BODY LENGTH | 0.870 INCHES MAXIMUM" |
ADAT | BODY WIDTH | 0.220 INCHES MINIMUM AND 0.310 INCHES MAXIMUM" |
ADAU | BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.185 INCHES MAXIMUM" |
AEHX | MAXIMUM POWER DISSIPATION RATING | 270.0 MILLIWATTS" |
AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS" |
AFJQ | STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS" |
AGAV | END ITEM IDENTIFICATION | SIGNAL PROCESSOR TYPE CM-442A/ALR-46(V)" |
CBBL | FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND ASYNCHRONOUS AND EDGE TRIGGERED AND HIGH SPEED AND POSITIVE OUTPUTS AND W/CLEAR AND W/ENABLE" |
CQSJ | INCLOSURE MATERIAL | CERAMIC AND GLASS" |
CQSZ | INCLOSURE CONFIGURATION | DUAL-IN-LINE" |
CQWX | OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC" |
CQZP | INPUT CIRCUIT PATTERN | 10 INPUT" |
CSSL | DESIGN FUNCTION AND QUANTITY | 1 FLIP-FLOP, D-TYPE AND 1 FLIP-FLOP, J-K, MASTER SLAVE" |
CZEQ | TIME RATING PER CHACTERISTIC | 35.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT" |
TEST | TEST DATA DOCUMENT | 15786-308842 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWI" |
ADAQ | BODY LENGTH | 0.870 INCHES MAXIMUM" |
ADAT | BODY WIDTH | 0.220 INCHES MINIMUM AND 0.310 INCHES MAXIMUM" |
ADAU | BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.185 INCHES MAXIMUM" |
AEHX | MAXIMUM POWER DISSIPATION RATING | 270.0 MILLIWATTS" |
AFGA | OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS" |
AFJQ | STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS" |
AGAV | END ITEM IDENTIFICATION | SIGNAL PROCESSOR TYPE CM-442A/ALR-46(V)" |
CBBL | FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND ASYNCHRONOUS AND EDGE TRIGGERED AND HIGH SPEED AND POSITIVE OUTPUTS AND W/CLEAR AND W/ENABLE" |
CQSJ | INCLOSURE MATERIAL | CERAMIC AND GLASS" |
CQSZ | INCLOSURE CONFIGURATION | DUAL-IN-LINE" |
CQWX | OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC" |
CQZP | INPUT CIRCUIT PATTERN | 10 INPUT" |
CSSL | DESIGN FUNCTION AND QUANTITY | 1 FLIP-FLOP, D-TYPE AND 1 FLIP-FLOP, J-K, MASTER SLAVE" |
CZEQ | TIME RATING PER CHACTERISTIC | 35.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT" |
TEST | TEST DATA DOCUMENT | 15786-308842 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWI" |